Be based on design of 8 of RISC technology small controller

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Article introduction is based on the design of 8 of RISC technology small controller and implementation. Basically include RISC instruction part choose; Take the design that points to unit, coding unit, executive unit; Take point to, coding, answer the implementation that writes skill of 3 class automation line. This are small controller includes 8 class hardware stack, 1 a 8 tally, tally spills over interrupt, 2 exterior interrupt source, 8 digit to occupy × of 16 input and output port, general purpose register, 2K the data of 16 program memory, 512 byte. The design is used but integrated Verilog language description, quartus Ⅱ software is emulated, test and verify of FPGA parts of an apparatus comes true. The ceaseless development of foreword   as microelectronics technology, of VLSI compositive spend and craft level rises ceaselessly, system of electron of will whole application is compositive in a chip (SoC) , already made the trend that contemporary electron system designs; Before Gao Fu is miscellaneous degree, of high cost embedded what construction of system can pass low cost is odd a chip implementation. On the other hand, complex but parts of an apparatus of process designing logic (CPLD) and spot but array of process designing door (FPGA) is compositive spend and rate rises ceaselessly, the function increases ceaselessly, development staff can use high-powered EDA to develop tool and hardware description language integratedly (HDL) gives complex electronic application system in the design inside short time. Current, embedded the system has gotten applied extensively in all trades and professions. Labour accuses, each domains such as communication, car, aerospace and military affairs can see embedded systematic form, and small controller (MCU) is embedded systematic core. Computer of collect of 1 compact instruction (RISC) 　 　 1.

1The structural feature of RISC and design principle cut instruction collect computer to have weak periodic sheet to dictate, the memory operation to register, find the structural trait of location means and simple statement form simply, its design a principle to be: ① chooses to use the statement with tall frequency, compensatory a few efficient instructions; The structure that ② dictates is simple, all instruction length is equal; ③ uses automation line technology, make as far as possible CPI = 1; ④ uses Load/Store to operate an instruction to visit memory; ⑤ uses general purpose register (GPR) structure; ⑥ is optimized compile, improve executive efficiency. 1.

CPI of 2 property factor and factor of executive time performance are the CPI of average clock periodicity that shows small controller dictates every (Cycles Per Instruction) : Total executive time T is the program: Executive time is the main index of small controller function. In 3 factors that affect T, clock frequency depends on hardware technology; The compositive structure of CPI and instruction collect and MCU is concerned; And instruction number is mixed by instruction collect compile technical decision. Want to make the function of small controller gets rising, optimizing an instruction to the collect, total instruction that reduces an order is counted and reduce CPI to be worth is the issue that designs main consideration. The small controller that the graph of construction of system of 2 small controller shows 1 times basically comprises by the following module: Memory of ① PROM program is unit (Program ROM) . Program memory capacity is 2K × 16. After systematic restoration, PC points to program tally program memory 000H is unit, the program begins to carry out from 000H place. Coding of ② IDEC instruction is unit (Instruction Decoder) . Instruction encoder undertakes coding to 16 of the input wide instructions, the address that outputs memory of register, data and read / write control signal. Operation of ③ ALU arithmetical logic is unit (Arithmetic Logic Unit) . ALU unit is the core part of MCU data processing, data width is 8, have add, decrease, logistic operation and shift function. ALU unit has 2 8 data inputs and a 8 data output, a carry is inputted, mark of a carry is outputted and 0 marks are outputted. Input of operation command code is 4, offer by coding unit. ④ REGS register is unit (Register) . 1 group 16 8 register, the high speed that is used at data is accessed. Register group has 2 data to output port and port of input of a data, read and address is apart, can undertake reading at the same time / keep an operation. Memory of ⑤ DRAM data is unit (Data RAM) . Include 4 paragraphs in all 512 byte (every paragraphs of 128 byte) data memory, direct addressability is 128 byte, indirect addressability is 256 byte, what control register PSW by order state is tall 2 position control paragraph choose an address. ⑥ CTRL controls unit (Control Unit) . The control center of whole MCU, the move of the control that basically dominates bus line of automation line operation, data and program tally. Additional, still include to interrupt, tally and stack control. ⑦ other. Defined 1 group of data to input 2 groups of port, data to output port, data wide all be 8; 2 exterior interrupt input INT0 and INT1; A 8 tally TIMER; Stack of stack of 7 rank order, can realize 7 class subprogram to call; A 8 order state controls register PSW. If each function is expressed 1. Everybody of watch 1 PSW functional 　 PSW.

7PSW.

6PSW.

5PSW.

4PSW.

3PSW.

2PSW.

1PSW.

RAM of 0 　 　 paragraph choose RAM Duan Xuanjin CIN reservation INT1 is interrupted allow tally to spill over interrupt INT0 allow to open / stop 　 of technology of tally Nextpage3 automation line 3.

Small controller of construction of automation line of 1 3 class is used take point to (IF) , carry out (EX) , time write (3 class of WB) automation line structure, if pursue 2. The main function of each phase is: Take point to class -- take out an instruction from inside program memory, undertake instruction coding at the same time, prepare register, memory read an address, read / write control signal; Executive class -- unit operation of data input ALU, prepare the address of register or memory at the same time; Time keep level -- the operation result that outputs ALU writes register or in memory. 3.

Competition of 2 automation line and solve control competition, the change that is worth by program PC finger is caused. Should carry out jump turn when the instruction, PC index value wants to be changed to executive level ability, this will make next extraction that pat show the operation makes mistake. Must insert a sky to handle NOP instruction by hardware at this moment, the reassume after the value that awaits PC finger is changed issues a statement. Data competes, by cause related the data between the instruction. Memory visit puts prevenient read-after-write relevant (Read After Write) , of an instruction write an operation to want to answer the ability that keep level to finish. When the content that if a back-to-back instruction needs to read,takes same address, must use side road (Bypassing) technology, from the output of ALU the result feedbacks to carry what dictate for below one to carry out class to use to the input of ALU directly. Small controller of 4 instructions collect and statement form dictates length is 16 fixed length, command code uses variable long structure. Command code is long have 4 (count operation instantly) , 5 (jump turn, register - memory operation) or 8 (register - register operation) . Supportive instruction covered statement of the basiccest MOV, ADD, SUB, AND, OR, XOR, and shift, all sorts of jumping turn the instruction. The instruction can not contain to clear centrally, take instead, be added oneself and decrease an instruction oneself, because these dictate,can replace by instruction of AND, XOR, ADD, SUB. In 51 series sheet piece in machine, the to clear of accumulator, take instead, be added oneself and reduce operation oneself (odd cycle) than accumulator - the logistic operation that counts instantly (double cycle) fast; And in the RISC small controller that realizing only periodic only statement, the to clear of register of usable and corresponding implementation of logistic operation instruction, take instead, be added oneself and reduce an operation oneself, do not have an influence to function. 5 logic are integrated, emulate and the Quartus II 2 that hardware realizes all module to all be in Altera company.

Integrated, emulation test carries 1 aspirant travel logic, the test and verify on the parts of an apparatus of FLEX10KE series FPGA that supporting memory comes true. 969 LE count logistic and integrated eventuate (Logic Elements) . It is one simple procedure below, if emulation weaveform pursues 3. 000: ADD R1, #01H; instruction is 1101H, r1 corresponding Pb outputs 　 001: MOV R2, pa; instruction is FE62H, r2 outputs 　 to Pc 002: Instruction of JMP 000H; is C000H, jump circularly the process that the data that mouth of the change that turns to be able to understand guiding principle of the PC when seeing the program is carried out from emulation weaveform, Pb increases the opening that reach Pa oneself conducts Pc mouth, the extraction that also can see a program roughly points to, carry out, answer those who write 3 class running water to carry out a process. Still can see at the same time carrying out jump turn dictate JMP hind inserts a sky automatically to operate NOP to dictate (FFFFH) . Epilogue looks integratedly with the result of emulation test from logic, this are small controller reached design target completely. The key of the design is the control of the implementation of 3 class automation line and data bus line. The design uses Verilog language description, readability is good, easily resource of increase and decrease and modification function, can apply at conveniently embedded in the system. Because time is brash,mix the level is finite, a lot of problems fail to consider, insufficient place adjures reader grant instruction. Origin: ? Does Pi wring Tan of Lai of  of stir-fry before stewing of ば of  of  of bad news of Lu of  Feng Kun? CNC Milling CNC Machining